Beebthernet
Well I have a name for my project of getting ethernet on to my BBC Microcomputer. Its now called Beebthernet. After some prototyping on copper strip-board and testing I revised the schematic for the interface.
The new schematic is below as is the almost completed interface. The LEDs and their resistors are not on the board. Clicking on an image will take you to the Flickr page where many of the images are annotated.
Unfortunately it doesn’t work. I can read data fine but I can’t write data. I looked at the bus and the data is getting to the module so I re-checked the timings. Normally peripherals are slower than the devices trying to read them so the issue is slowing the processor or bus down. However this is a modern peripheral and at least a 30 year old processor design. The timing specification for a 2MHz 6502 says that the data bus will be stable ay a minimum of 110ns after the clock E2 goes high. Since reads and writes are made when E2 is high the /RD and /WR lines, which are generated from E2 and the R/W line, will go low sooner than that. The specification for the WIZ812MJ says that the maximum time take for the data lines to stabilize is 18ns. I.e. the data bus doesn’t stabilize in time. I need to work out a way of delaying the write line signal change by 100ns.
So I then knocked up an SPI version of the interface on breadboard and connected it to the User IO port, which is connected to port B of the 6522 VIA, on the BBC Micro. I wrote a bit banging routine to read and write to the WIZ810MJ in SPI mode which, although is the slowest mode available, will work what ever the speed of the IO. It worked! I managed to set the MAC address and interface, netmask and gateway IP addresses and pinged the device from my MacBook. The breadboard set up and results of the ping test are below. Again the images are annotated on Flickr.
Tags: Acorn, BBC Micro, BBC Microcomputer, Beeb, Electronics
September 15th, 2009 at 12:58 pm
Might I suggest a 2-phase clock signal? Run a 4-Mhz clock through through a couple D flip-flops and you can get yourself 2 2-Mhz clocks 90 deg. out of phase. Perhaps that will not work for your particular setup, but I figured I would suggest it anyway. I was able to recall a project I found which used such a setup (PDF warning): http://www.stevechamberlin.com/cpu/schematics.pdf. The last page contains the clock generator schematic.
- Cheers
September 15th, 2009 at 2:35 pm
Useful link that. Not sure your suggestion will be useful for this project but I’ll study that schematic as there seem to be ideas I can use
Thanks.
March 15th, 2010 at 6:29 pm
If it works via the slow I/O port, it should work via the 1MHz bus, avoiding preventing the Tube port being used to connect a Tube system. Alternatively, if you do want to go down the line of connecting to the Tube port, ensure you fully decode A4-A6 and only respond when not in Tube space and provide a pass-though conntector for access outside your space.